STX104(-ND) Firmware Upgrade Kit

Trigger Start. 14 selectable events.

Trigger Stop. 15 selectable events.

Trigger Sync. Trigger Sync. 12 selectable events.

Synchronization via external signal sources (i.e. 60Hz)

Three possible triggering sequences.

Trigger delay timer

More IRQ lines supported including IRQ9, IRQ10, IRQ11, IRQ12, IRQ14 and IRQ15.

Two additional interrupt sources. Each has 13 selectable events.

Interrupt source status available at one location for faster interrupt service routines.

Interrupt threshold counter for multiple events per interrupt. 13 selectable events.

Interrupts can be synchronized to trigger start event.

Number of analog input data blocks per FIFO interrupt is now adjustable (two methods possible).

Polarity control.

Polarity control.

Long (200 nSec) or short (100 nSec) deglitch filter.

Sampling sources. 11 selectable source (all legacy functions have been preserved).

32-bit intra-sample burst timer with resolution to 25 nanoseconds for improved timing between samples in ADC-burst mode.

Non-synchronization/synchronization with trigger start. In other words, sample timing can remain at fixed intervals regardless of triggering start event or be synchronized to the triggering start event, respectively.

32-bit frame timer with resolution 25 nanoseconds. ADC-Burst sample sequences or ADC-sampling can be controlled by this 32-bit timer.

32-bit burst (intra-sample) timer with resolution to 25 nanoseconds. This timer is used to adjust the timing between ADC-samples during an ADC-Burst operation (i.e. one or more channels collected at a time).

32-bit maximum frame counter. This counter can be used to count the number of ADC-samples or ADC-bursts and when the count is reached a user defined limit, this event can be used to generate interrupts or trigger stop situations. Thus, it is now possible to collect N-number of samples into the large FIFO memory and stop collecting after a given interval of time with little software overhead.

FIFO status values are now properly latched and in addition, the block count will not mis-report values.

DIN3 and DIN1 one can reverse the swapped positions of these inputs.

An additional high speed FIFO can be enabled between STX104 main memory and the ISA bus, further reducing and/or eliminating wait state (IOCHRDY) conditions, further enhancing overall ISA bus data throughput.

All status registers are properly latched to prevent change in values during a bus read cycle.

I/O Read line is digitally filtered to support noisy ISA bus problems and eliminate the possibility of dropped analog input data.

Indexed register array banked over the 8254 registers. This opens the door for many new functions as described above.

Moving average filter is has been corrected to present channel data in the proper order.