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Name |
Description |
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- Single ADC-sample per analog input sample event.
- Analog input sampling events enhanced from 3 to 13 possible sources.
- Supports DMA (see note).
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- ADC-sample per analog input sample event.
- ADC-burst (one or more channels collected) per analog input sample event. Timing between ADC-samples within a burst are adjustable from 5 microseconds to 53 seconds to 25 nanosecond resolution.
- Analog input sampling events enhanced from 3 to 13 possible sources.
- Large FIFO depth allows for greater interrupt latency or readout latency.
- Supports DMA (see note).
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- CPU read-out N-blocks of data per unit of time (i.e. CPU-burst reads)
- Sample timing and intra-sample timing in ADC-burst modes adjustable to 25 nanosecond resolution.
- FIFO interrupt generated interrupts and events very flexible to support optimal CPU bursting (ultimately dependent on other CPU overhead or rhythmic behavior such as flash drives).
- Data fragment buffer reduces PC/104 generated IOCHRDY or wait conditions, further enhancing PC/104 data bus throughput.
- Large FIFO depth enhances the time decoupling between CPU activities and precise sample timing.
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- Start-Trigger to begin sampling, then Stop-Trigger to stop sampling. Repeat sequence.
- Large FIFO depth offers ability to collect large groups of data with a post-readout scheme.
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- Start-Trigger to begin sampling, stop sampling when N-samples/-Frames reached (i.e. Stop-Trigger event).
- Large FIFO depth offers set it and forget it methodology, thus drastically reducing CPU software monitoring overhead.
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