D7 

D6 

D5 

D4 

D3 

D2 

D1 

D0 

X 

X 

X 

X 

X 

X 

CT_SRC0 

GCTRL 

D7 

D6 

D5 

D4 

D3 

D2 

D1 

D0 

ABL3 

ABL2 

ABL1 

ABL0 

X 

X 

CT_SRC0 

GCTRL 

NAME 

DIRECTION 

DEFAULT 

DESCRIPTION 

ABL[3:0] 

w 

- 

ADC-Burst Length. Determines the number of conversions per trigger when in burst mode. One to sixteen samples (single-ended) or up to eight channels (differential) in a burst. When not in Burst mode, then these bits have no function. The burst length is only used in the DAS1602 compatibility mode.

If ABL[3:0]=0x0, then 1-channel burst is performed. If ABL[3:0]=0xF, then 16-channel ADC-burst is performed.
 

CT_SRC0 

w 

1 

Counter 0 Clock Source:
1 = Counter 0 Clock Source is a 100KHz on-board reference frequency. CT_SRC0 (J7.4) gates this signal. When this bit is high (default), the 100KHz signal runs, otherwise the 100KHz clock is stopped.
0 = Counter 0 Clock Source to Counter 0 is an inverted polarity copy of CT_CLK0 input. CT_CLK0 is connected to a 10K ohm pull-up resistor.
 

GCTRL 

w 

0 

Counters 1 and 2 gate control:
0 = Counters 1 and 2 run freely with no gating.
1 = Counters 1 and 2 are gated by DIN0 (J7.12). DIN0 is connected to a 10K ohm pull-up resistor.
 

X 

- 

- 

Don't Care