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Digital Inputs (Offset=3)

Digital Input Register.

Register Layout

Offset=0x3, Byte 0.

D7 
D6 
D5 
D4 
D3 
D2 
D1 
D0 
CM1 
CM0 
DIN3 
DIN2
GATE0 
DIN1 
DIN0 
Bit Definitions
NAME 
DIRECTION 
DEFAULT 
DESCRIPTION 
CM[1:0] 
M0 
Compatibility mode. These bits are set to zero for DAS16jr/16 mode. These bits are set to one for DAS1602 mode compatibility. 
Don't Care 
DIN[3:0] 
0000 
Digital Inputs.
DIN0 also functions as an ADC external trigger input. As a trigger input, it is deglitched by an internal match-filter and requires a minimum pulse width of no less than 200nS. See the Interrupt Summary section for further functionality.
DIN2 also functions as counter-zero gate input. 

 

DIN1 and DIN3 swapped to their correct positions

BIT NAME 
DIRECTION 
CONNECTOR PIN POSITION 
PHYSICAL I/O TYPE 
DIN3 
<--- 
J7.11 
TTL Input 
DIN2 
<--- 
J7.10 
TTL Input 
DIN1 
<--- 
J7.9 
TTL Input 
DIN0 
<--- 
J7.12 
TTL Input 

 

Classic STX104 Configuration (supporting existing customers, Default mode)

BIT NAME 
DIRECTION 
CONNECTOR PIN POSITION 
PHYSICAL I/O TYPE 
DIN3 
<--- 
J7.9 
TTL Input 
DIN2 
<--- 
J7.10 
TTL Input 
DIN1 
<--- 
J7.11 
TTL Input 
DIN0 
<--- 
J7.12 
TTL Input 

Digital TTL inputs.

Copyright © 1997-2008 by Apex Embedded Systems. All rights reserved. Updated on Wednesday, April 02, 2008.
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