Analog Input Burst Timer (Index=40, RB='1')

Analog Input Burst Timer. Adjusts timing between samples during ADC-burst mode.

Index=0x28, Byte 0. Index=0x28, Word 0. RB='1'.

D7	D6	D5	D4	D3	D2	D1	D0
AIBT7	AIBT6	AIBT5	AIBT4	AIBT3	AIBT2	AIBT1	AIBT0

Index=0x29, Byte 1. Index=0x28, Word 0. RB='1'.

D15	D14	D13	D12	D11	D10	D9	D8
AIBT15	AIBT14	AIBT13	AIBT12	AIBT11	AIBT10	AIBT9	AIBT8

Index=0x2A, Byte 2. Index=0x2A, Word 1. RB='1'.

D23	D22	D21	D20	D19	D18	D17	D16
AIBT23	AIBT22	AIBT21	AIBT20	AIBT19	AIBT18	AIBT17	AIBT16

Index=0x2B, Byte 3. Index=0x2A, Word 1. RB='1'.

D31	D30	D29	D28	D27	D26	D25	D24
AIBT31	AIBT30	AIBT29	AIBT28	AIBT27	AIBT26	AIBT25	AIBT24

Bit Definitions

NAME	DIRECTION	DEFAULT	DESCRIPTION
AIBT[31:0]	rw	0x00000000

Description

Adjusts the time between ADC-samples in a ADC-Burst mode. In legacy mode this is 5 microseconds.

The actual time interval is calculated as:

ADC_Frame_Time = AIBT * ( 25 nSec ) + ( 5000 nSec ).

Where 0 <= AIBT <= 2147483648.

Thus, the ADC burst time is adjustable from 5 microseconds to 53.68 seconds in 25 nanosecond steps.

Range: 5 uSec to 53.68 Seconds.

Resolution: 25 nanoseconds.

How to determine optimal ADC-Burst timing value? Since the ADC input is multiplexed, the speed limitation is the overall RC time constant or settling time to achieve 16-bit resolution. The equation below describes how to determine minimum intra-burst timing.

Settling Time in ADC-Burst Mode:

Some background. A burst, once started will sample from first_channel to last_channel in 5uS intervals in legacy mode. So, eight channels will take 40uS to complete. The trigger for the next burst can actually come early (i.e. before the last sample completes) and it should start the next burst immediately as if one is continuously sampling at 5uS/sample.

As with all multiplexed front-ends, it is desirable to keep the source impedance of the signals driving each of the inputs as low as possible to minimize cross-talk (i.e. more specifically settling time). Differential inputs have 47pF input capacitance and single ended inputs have 27pF input capacitance (we tend to lean on the high side or worse case). So, to keep

signal settle times to less than 1 LSB requires:

Rmax <= ( settle_time ) / [ Cin * bits_resolution * ln(2) ]

<= 4uS / [ 47pF * 16 * ln(2) ]

<= 7674 ohms.

You will want to keep the devices driving the STX104 inputs with source impedance of less than 8K ohms when operating in Burst mode at its maximum speed and assuming no other source of input capacitance (short cables, for example).

This equation above comes from:

V(t) = Vf + ( Vi - Vf ) exp(-t / RC )

in which you go from maximum to minimum input voltages

(i.e. +10V to -10V and settle to within 1 LSB).

Note that in the above calculation we set the settle time to within 1 LSB over 4uS time frame; we could go as far as 5uS, but 4uS gives us a little extra margin.

Increasing Settle Time in ADC-Burst Mode:

To increase settle time, you have to set the Analog Input Burst Timer to a non-zero value. Here is an example with a sensor with a source impedance of 10K ohms.

Settle_time = Rin * [ Cin * bits_resolution * ln(2) ]

= 10K * [ 300pF * 16 * ln(2) ]

= 34uS

Thus, the Analog Input Burst Timer Register should be set to:

AIBT = [ ( 34 uSec ) - ( 5 uSec ) ] / 25 nSec = 1160 or 0x00000488.