FIFO Status MSB (Offset=10)

FIFO Status MSB Register.

Offset=0xA, Byte 0. FIFO Status MSB Register.

D7	D6	D5	D4	D3	D2	D1	D0
FIFO_INT	DFR (a)	FF	FE	FBR11	FBR10	FBR9	FBR8

Offset=0xF, Byte 0. FIFO Status LSB Register.

D7	D6	D5	D4	D3	D2	D1	D0
FBR7	FBR6	FBR5	FBR4	FBR3	FBR2	FBR1	FBR0

Bit Definitions

NAME	DIRECTION	DEFAULT	DESCRIPTION
FIFO_INT	r	0	FIFO Data Interrupt. An interrupt will occur for 512 or more samples queued in the FIFO in legacy mode. If FIBLK[1:0] not zero (refer to Interrupt Source Select), then an interrupt will be generated with larger block counts. This bit can be polled and/or use to generate an interrupt to the CPU (setting FIE bit true in the ADC Control Register). 0 = No FIFO interrupt (default at reset or power-up) 1 = FIFO interrupt active. To Clear Interrupt Register, write any value at Clear Interrupt Register.
DFR	r	0	Data Fragment Ready Flag: 0 = Data Fragment not ready (default at reset or power-up) 1 = Data Fragment ready.
FF	r	0	FIFO Full Flag. 0 = FIFO not full (default at reset or power-up) 1 = FIFO full/overflow has occurred.
FE	r	1	FIFO Empty Flag. 1 = Empty (default at reset or power-up) 0 = FIFO not empty, data is present
FBR[11:0]	r	0x000	FIFO Data Blocks Remaining. This provides a mechanism for measuring amount of data remaining within the FIFO. Each block is 256 samples. For example, if FBR=0x05 then at least 1,280 samples remain to be read out of the STX104 FIFO. If FBR=0x00 and FE=’0’ then there are less than 256 samples remaining to be read out of the FIFO. When FBR>0, use REP INSW to read in 256 samples at a time (1 block). When FBR=0, use a software loop that monitors the FE bit while reading in the samples until the FIFO is empty.

Description

The FIFO Status Registers are only available when FIFO Superset is Enabled (M1 jumper installed).

The number of data blocks used in order to generate a FIFO interrupt (FIFO_INT), can be adjusted via the FIBLK[1:0] bits in the Interrupt Source Select or the Interrupt Threshold registers. In many cases utilizing the FIBLK[1:0] bits is sufficient and keeps the Interrupt Threshold Register available for other functions.

IOCHRDY and FIFO DATA FRAGMENT

In order to avoid using IOCHRDY or I/O bus wait states the STX104 incorporates an intermediate data buffer to support CPU-burst reads which avoid changing the state of the IOCHRDY line.

When DFR is true, then the data fragment is ready to be read out, typically using the Insw() function which incorporates the REP INSW instruction.

There is theoretically no limit, other than the maximum size of the entire STX104 FIFO memory, on the number of consecutive CPU reads that can occur. However, by limiting the number of samples readout by the CPU using the Insw() to approximately the size of the Data Fragment buffer, one can avoid I/O bus wait states and further improve bus bandwidth.

It should be further stated that the CPU can still readout data at any rate along with any ADC sampling mode. In fact, the data fragment buffer will be used in nearly all cases, thus bus wait states become a thing of the past. The only case where I/O bus wait states will exist are cases where the number of samples read out by the CPU in a CPU-bursting readout (i.e. Insw() function) exceeds the data fragment buffer size.

FIFO CLEAR or RESET

Note that writing to the Channel Register will reset the FIFO.

See Also

Example

Below is an example of properly reading the FIFO status. This applies to firmware revisions specifically before 080214H (although it will still work fine for any revision 080214H or higher).

Copy Code

static int stx104_fifo_status_blocks[STX104_BOARDS_COUNT_MAX];
static unsigned char stx104_fifo_status_full[STX104_BOARDS_COUNT_MAX];
static unsigned char stx104_fifo_status_empty[STX104_BOARDS_COUNT_MAX];


/*****************************************************************
/                                                      FIFO STATUS
/ Revision History:
/ 15JAN07 - read FIFO status twice to remove the possibility
/           of reading an incorrect value due to FIFO status
/           changing during a 25nSec interval.
*/
#define STX104_FIFO_STATUS_READ_COUNT_MAX   1
void STX104_FIFO_Status( int board )
{
    union { unsigned int value; unsigned char octet[2]; } ff_stat[STX104_FIFO_STATUS_READ_COUNT_MAX+1];
    unsigned int fbr_blocks;
    unsigned int fbr_blocks_minimum;
    unsigned char i;

    fbr_blocks_minimum = 0x0FFF;

    for ( i=0; i<=STX104_FIFO_STATUS_READ_COUNT_MAX; i++ )
    {
        ff_stat[i].octet[0] = inp( stx104_base_address[board] + STX104_FIFO_DATA_STATUS );
        ff_stat[i].octet[1] = inp( stx104_base_address[board] + STX104_FIFO_FLAGS );

        fbr_blocks = ff_stat[i].value & 0x0FFF;
        if ( fbr_blocks < fbr_blocks_minimum )
        {
            fbr_blocks_minimum = fbr_blocks;
        }
    }
    stx104_fifo_status_blocks[board] = (int) fbr_blocks_minimum;

    if ( (ff_stat[STX104_FIFO_STATUS_READ_COUNT_MAX].value & 0x1000) != 0x0000) stx104_fifo_status_empty[board] = true;
    else stx104_fifo_status_empty[board] = false;
    if ( (ff_stat[STX104_FIFO_STATUS_READ_COUNT_MAX].value & 0x2000) != 0x0000) stx104_fifo_status_full[board] = true;
    else stx104_fifo_status_full[board] = false;
}

For firmware revisions 080214H or higher:

Copy Code

static int stx104_fifo_status_blocks[STX104_BOARDS_COUNT_MAX];
static unsigned char stx104_fifo_status_full[STX104_BOARDS_COUNT_MAX];
static unsigned char stx104_fifo_status_empty[STX104_BOARDS_COUNT_MAX];


/*****************************************************************
/                                                      FIFO STATUS
*/
void STX104_FIFO_Status( int board )
{
    union { unsigned int value; unsigned char octet[2]; } ff_stat;

    ff_stat.octet[0] = inp( stx104_base_address[board] + STX104_FIFO_DATA_STATUS );
    ff_stat.octet[1] = inp( stx104_base_address[board] + STX104_FIFO_FLAGS );

    stx104_fifo_status_blocks[board] = ff_stat.value & 0x0FFF;

    if ( (ff_stat.value & 0x1000) != 0x0000) stx104_fifo_status_empty[board] = true;
    else stx104_fifo_status_empty[board] = false;
    if ( (ff_stat.value & 0x2000) != 0x0000) stx104_fifo_status_full[board] = true;
    else stx104_fifo_status_full[board] = false;
}

Group

Links

Contents | Index | Home

What do you think about this topic? Send feedback!