What are the Benefits of using the STX104? The STX104 has the following benefits: 

• One mega-sample FIFO data storage provides continuous data streaming from ADC to CPU with reduction in interrupt overhead and relaxation of interrupt latencies. 

• 200,000 Samples per second aggregate for analog inputs 

• Analog input 16-Sample moving average filters for data noise reduction 

• Compatible with DAS16jr/16 and DAS1602 for using existing 3rd party drivers 

• 16-bit data read (ADC data) operations double effective PC/104 bus bandwidth 

• 16-bit data write (DAC data) operations reduce software overhead 

• Use REP INSW (286 or higher CPU) to read-in blocks of ADC data from FIFO further increasing bandwidth and reducing complexity. 

• Burst mode with only one interrupt generated per complete scan, thus reducing interrupt overhead and increasing effective throughput. 

• One interrupt per 512-samples is possible in FIFO mode 

• On-board LED to indicate that the STX104 is being addressed. By observing the LED you can quickly determine system activity. 

• Polarized locking I/O connector. This eliminates board failures due to incorrect connector orientation. 

• Extremely low DC drift 

• External trigger input (DIN0) is deglitched preventing unwanted ADC triggers. Minimum valid pulse width required is 200nS. 

• Industrial temperature range from -40^oC to +85^oC 

• No tantalum capacitors or electrolytic capacitors used in the design 

• Single +5V supply operation 

• Supports both 8- and 16-bit PC/104 data busses
• Supports 10-bit or 16-bit I/O addressing via jumper using jumper M4. DAS1602 register set located at base_address + 0x400 are also now relocated in an indexed register spaced within the 10-bit address space.
• Improved I/O wait states as well as wait state reduction supporting higher speed CPUs along with improved PC/104 bus throughput.
• New triggering subsystem
  • Trigger Start. 14 selectable events.
  • Trigger Stop. 15 selectable events.
  • Trigger Sync. Trigger Sync. 12 selectable events.
  • Synchronization via external signal sources (i.e. 60Hz)
  • Three possible triggering sequences.
  • Trigger delay timer.
• Interrupts
  • More IRQ lines supported including IRQ9, IRQ10, IRQ11, IRQ12, IRQ14 and IRQ15.
  • Two additional interrupt sources. Each has 13 selectable events.
  • Interrupt source status available at one location for faster interrupt service routines.
  • Interrupt threshold counter for multiple events per interrupt. 13 selectable events.
  • Interrupts can be synchronized to trigger start event.
  • Number of analog input data blocks per FIFO interrupt is now adjustable (two methods possible).
• Digital Outputs
  • Polarity control.
• Digital Inputs
  • Polarity control.
  • Long (200 nSec) or short (100 nSec) deglitch filter.
• Analog Inputs
  • Sampling sources. 11 selectable source (all legacy functions have been preserved).
  • 32-bit intra-sample burst timer with resolution to 25 nanoseconds for improved timing between samples in ADC-burst mode.
  • Non-synchronization/synchronization with trigger start. In other words, sample timing can remain at fixed intervals regardless of triggering start event or be synchronized to the triggering start event, respectively.
  • 32-bit frame timer with resolution 25 nanoseconds. ADC-Burst sample sequences or ADC-sampling can be controlled by this 32-bit timer.
  • 32-bit burst (intra-sample) timer with resolution to 25 nanoseconds. This timer is used to adjust the timing between ADC-samples during an ADC-Burst operation (i.e. one or more channels collected at a time).
  • 32-bit maximum frame counter. This counter can be used to count the number of ADC-samples or ADC-bursts and when the count has reached a user defined limit, this event can be used to generate interrupts or trigger stop situations. Thus, it is now possible to collect N-number of samples into the large FIFO memory and stop collecting after a given interval of time with little software overhead.
• Other improvements
  • FIFO status values are now properly latched and in addition, the block count will not incorrectly report values.
  • DIN3 and DIN1 the user can reverse the swapped positions of these inputs.
  • An additional high speed FIFO can be enabled between STX104 main memory and the ISA bus, further reducing and/or eliminating wait state (IOCHRDY) conditions.
  • All status registers are properly latched as well to prevent change in values during a bus read cycle.
  • I/O Read line is digitally filtered to support noisy bus problems and eliminate the possibility of dropped analog input data.
  • Indexed register array banked over the 8254 registers. This opens the door for many new functions as described above.
  • Moving average filter has been corrected to present channel data in the proper order.

• 8254 Counter/Timer is also available within the indexed register set. This allows software access to all registers when the indexed register set is enabled.

Please note that all of the new registers are designed such that if they are not configured, everything defaults to the classic modes of operation. Thus, existing software will function without modification. Writing values to the new registers enhances operations.

Benefits and Features