ADC Control (Offset=9)

ADC Control Register

Offset=0x9, Byte 0. EIS='1', Please refer to the Interrupt Source Select Register.

D7	D6	D5	D4	D3	D2	D1	D0
IES3	IES2	IES1	IES0	FIE (a)	DMAE	ALSS1 (b)	ALSS0 (b)

Offset=0x9, Byte 0. EIS='0' (default), Please refer to the Interrupt Source Select Register.

D7	D6	D5	D4	D3	D2	D1	D0
AIE	INTS2	INTS1	INTS0	FIE (a)	DMAE	ALSS1 (b)	ALSS0 (b)

(a) FIFO Superset Enabled (jumper M1 installed), otherwise the bit is a don’t care.

(b) Was previously named TSx. The term “ADC-sample” or “ADC-burst” is used to replace the term “trigger”, since triggering takes on a more generalized definition.

Bit Definitions

NAME	DIRECTION	DEFAULT	DESCRIPTION
IES[3:0]	rw	0000	Interrupt enhanced select (available only in Enhanced Register Set Mode): 0000 = Not valid, interrupts disabled (default) 0001 = Not valid, interrupts disabled 0010 = IRQ9/2 (IRQ2 for 8-bit or XT, IRQ9 for 16-bit or AT) 0011 = IRQ3 0100 = IRQ4 0101 = IRQ5 0110 = IRQ6 0111 = IRQ7 1000 = Not valid, interrupts disabled 1001 = IRQ9/2 (IRQ2 for 8-bit or XT, IRQ9 for 16-bit or AT) 1010 = IRQ10 1011 = IRQ11 1100 = IRQ12 1101 = Not valid, interrupts disabled 1110 = IRQ14 1111 = IRQ15
AIE	rw	0	ADC Interrupt Enable. 0 = Disable interrupt (default) 1 = Enable interrupt
INTS[2:0]	rw	000	Interrupt select: 000 = Not valid, interrupts disabled (default) 001 = Not valid, interrupts disabled 010 = IRQ2 011 = IRQ3 100 = IRQ4 101 = IRQ5 110 = IRQ6 111 = IRQ7
FIE	rw	0	FIFO Interrupt Enable (only when jumper M1 is installed): 0 = Disable FIFO interrupt (default) 1 = Enable FIFO interrupt
DMAE	rw	0	Direct Memory Access (DMA) enable: 0 = Disable DMA transactions (default) 1 = Enable DMA transactions The DMA request lines are tri-stated until the DMA bit is enabled, thus allowing multiple DMA devices to share the selected DMA channel provided that they are not enabled at the same time.
ALSS[1:0]	rw	00	ADC-Sample or ADC-Burst Legacy Sampling Select: 0X = Software (default) 10 = DIN0 rising/falling edge 11 = 8254 Counter 1 & 2 Pacer CT_OUT2 rising edge
X	-	-	Don’t Care

Description

The ADC Control Register is used to configure interrupts, select DMA mode and select ADC trigger source.

See Interrupt Summary for more information on interrupts.

DMA NOTE

We strongly encourage you to use the REP INSW instruction (or Insw() function in Linux) as it performs better than DMA and is substantially simpler to set up and use. Note that DMA performs I/O to memory transfers a byte at a time (DMA 1 and DMA 3 are byte wide transfers) while REP INSW performs I/O to memory transfers a word at a time. If you are designing a real-time system, you will have better timing control over your system by using REP INSW instruction over DMA. Since processor generated I/O cycles are faster than DMA generated cycles (typically 350ns versus 800ns), data transfer can take place faster than DMA. Note that 8-bit bus transactions (including DMA) are typically at least twice as long as 16-bit bus transactions; this alone is reason enough to avoid DMA.

When DMA is enabled, the 1 mega-sample FIFO is used internally.

In DMA mode, receiving a terminal count from the CPU will generate an interrupt, if the interrupt is enabled. If you are in DAS1602 mode (jumper M0 is installed), receiving a terminal count will set the Conversion Disable bit to false, thus disabling any additional ADC triggers (or sampling). Writing 0x00 to the Conversion Disable Register will allow ADC sampling to continue.

In order to use DMA, you must set up the computer’s DMA controller and page registers before enabling DMA on the STX104 board.

The speed of any ISA bus I/O transaction is dependent on the CPU ISA bus speed which is usually set in the BIOS setup; use this setting with caution as it may affect performance of other cards and/or can cause data loss. This is usually available on many CPU cards.